Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to make vhdl testbench for mux 4 to 1 and inputs are 4bits and output is 4bit

Hi! I have problem to make vhdl testbench for mux4/1 witch have 4bit inputs I0 I1 I2 I3 and 4bit output mux_out and select inputs are KO and K1. REMARK: I0 : in std_logic_vector (3 do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

I dont understand.

Please post some code.

--- Quote End ---

I think the post means that they want to test part of the design(the mux).

so if that is the case either test the mux alone as a separate module with its i/o interface exposed out, or just use full design and temporarily disconnect drive on mux inputs and drive them in the testbench