How to make a rtl simulation of design using megafunctions

You will be better off in the long term (IMO) learning to use modelsim yourself.

a .do file is just a TCL file (ie. list of commands) for modelsim to run:

vcom = vhdl compile (vlog = verilog compile)

vlib = create library

vmap = map a library to a specified path

These are the 3 commands you end up using the most and should get you by in most situations.

You can find all of the arguments listed in the command reference manual for modelsim.

Modelsim requires you write a testbench for any design. This way you have far more control over the unit under test.