How to make a rtl simulation of design using megafunctions

Thanks for your fast response Tricky.

I am still tryng to be able to simulate my local project/design in rtl mode before including it in the large one, as up to now I was only able to simulate it in the gate level.

I am launching the simulation from quartus in the same (small) project, changing the quartus compiling flow in the task window: Analysis->Fitter->TimeQuest->Netlist->Gate Level Simulation OR Analysis->RTL Simulation.

Two different .do files (attached) are generated by quartus and compiled by the simulator. While in the gate level the top hierarchy block, DCFIFO.vho, is created and I know how to access the input/output ports, in the rtl mode only lpm_mux and lpm_compare blocks are compiled...

I expeted quartus do all the job for each simulation flow (libraries, etc) but it seems i have to say quartus to start the rtl simulation from the top hierarchy block?