How to make a rtl simulation of design using megafunctions

have you included all of the generated files in your larger project?

how are you simulating? are you using quartus or have you written a .do file for the compilation? same question as above - have you included all the source files in your larger .do file to ensure vcom is run on the larger project.

have you compiled everything into the correct libraries?

what errors are you getting?

simulating in gate mode - bleugh - best avoid at all costs...