How to make a averager in VHDL

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That will be sign extension, ensuring that the slices arrays stay +ve or -ve correctly.

It reads better if you use the resize() function.

Looking at that code, it wont build the adder tree as I expect it, it just creates FirLength-1 output values (you usually end up with a single output).

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Yes, but I dont know the resize() function. And maybe the CSRealReg(FirLength-1) is the output which I want . If you're interesting the complete vhdl code you can see it in the attchment, Tricky. Thanks for your help.