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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to make a averager in VHDL

I have just readed a piece of VHDL code. It is used to average the signal value from AD(14 bit). The code i write below here： process(CLK80) begin if(CLK80'event and CLK80='1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

That will be sign extension, ensuring that the slices arrays stay +ve or -ve correctly.

It reads better if you use the resize() function.

Looking at that code, it wont build the adder tree as I expect it, it just creates FirLength-1 output values (you usually end up with a single output).