How to make a averager in VHDL

hi kaz！

Maybe I can ask you another VHDL code after this one. The data which is summed will be taken into a digital filter. The code is shown below:------------------- FIR FILTER ------------------

process(CLK80)

begin

if (CLK80'event and CLK80='1') then

if (DFTrigCReg='1') then

for I in 0 to firLength-1 loop

CQRealReg(I) <= avSigCReg(9)(17 downto 4) * DFcoeff(I);

end loop;

CSRealReg(0) <= CQRealReg(0)(23) & CQRealReg(0)(21 downto 0);

for I in 1 to firLength-1 loop

CSRealReg(I) <= CSRealReg(I-1) + (CQRealReg(I)(23) & CQRealReg(I)(21 downto 0));

end loop;

end if; --

end if; -- CLK

end process;

I think the DFcoeff is filter coefficient. But why the designer do the process like this" CSRealReg(0) <= CQRealReg(0)(23) & CQRealReg(0)(21 downto 0);"