--- Quote Start ---
Yup, write a testbench and get simulating.
But you dont really specify exactly what you want? what exactly are you averaging?
Notes on your code:
- You dont show the whole code, so we cannot see signal declarations
- WHy have you got a for loop summing together things?
- This code looks messy
A moving window average is easily acheived with a shift register and an adder tree, with a divider on the end. If the window is 2^n wide, all you need to divide is drop the n LSBs (with a possible rounding stage)
--- Quote End ---
I didn't show the whole code because it's very long.This code is writen by others and I just want to know what exactly it work and use it in my work. I have writen a copy for simulation. I will put it below.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity Averager is
port(CLK80: in std_logic;
sigCReg: in signed(13 downto 0);
SigSReg: in signed(13 downto 0);
samplingTriggerReg: in std_logic;
sigCLatchReg: in std_logic;
sigSLatchReg: in std_logic;
dfTrigSReg :out std_logic ;
dftrigCReg: out std_logic;
WS0: out signed(17 downto 0);
WS1: out signed(17 downto 0);
WS2: out signed(17 downto 0);
WS3: out signed(17 downto 0);
WS4: out signed(17 downto 0);
WS5: out signed(17 downto 0);
WS6: out signed(17 downto 0);
WS7: out signed(17 downto 0);
WS8: out signed(17 downto 0);
WS9: out signed(17 downto 0)
);
end Averager;
architecture Behavioral of Averager is
signal avCStateReg, avSStateReg: std_logic_vector(4 downto 0):="00000";
type avSig is array (0 to 9) of signed(17 downto 0);
signal avSigSReg,avSigCReg: avSig;
begin
process(CLK80) begin
if(CLK80'event and CLK80='1') then
if(samplingTriggerReg='1') then -- synchronization with the sampling trigger
avCStateReg <= "00000";
else
case avCStateReg is
when "00000"=> if(sigCLatchReg='1') then avCStateReg<="00001"; end if;
when "00001"=> if(sigCLatchReg='1') then avCStateReg<="00011"; end if;
when "00011"=> if(sigCLatchReg='1') then avCStateReg<="00111"; end if;
when "00111"=> if(sigCLatchReg='1') then avCStateReg<="01111"; end if;
when "01111"=> if(sigCLatchReg='1') then avCStateReg<="11111"; end if;
when "11111"=> if(sigCLatchReg='1') then avCStateReg<="11110"; end if;
when "11110"=> if(sigCLatchReg='1') then avCStateReg<="11100"; end if;
when "11100"=> if(sigCLatchReg='1') then avCStateReg<="11000"; end if;
when "11000"=> if(sigCLatchReg='1') then avCStateReg<="10000"; end if;
when "10000"=> if(sigCLatchReg='1') then avCStateReg<="00000"; end if;
when others => avCStateReg<="00000";
end case;
end if;
end if;
end process;
dfTrigCReg <= '1' when avCStateReg="10000" else '0';
process(CLK80) begin
if(CLK80'event and CLK80='1') then
if(samplingTriggerReg='1') then -- synchronization with the sampling trigger
avSStateReg <= "00000";
else
case avSStateReg is --gray counter?
when "00000"=> if(sigSLatchReg='1') then avSStateReg<="00001"; end if;
when "00001"=> if(sigSLatchReg='1') then avSStateReg<="00011"; end if;
when "00011"=> if(sigSLatchReg='1') then avSStateReg<="00111"; end if;
when "00111"=> if(sigSLatchReg='1') then avSStateReg<="01111"; end if;
when "01111"=> if(sigSLatchReg='1') then avSStateReg<="11111"; end if;
when "11111"=> if(sigSLatchReg='1') then avSStateReg<="11110"; end if;
when "11110"=> if(sigSLatchReg='1') then avSStateReg<="11100"; end if;
when "11100"=> if(sigSLatchReg='1') then avSStateReg<="11000"; end if;
when "11000"=> if(sigSLatchReg='1') then avSStateReg<="10000"; end if;
when "10000"=> if(sigSLatchReg='1') then avSStateReg<="00000"; end if;
when others => avSStateReg<="00000";
end case;
end if;
end if;
end process;
dfTrigSReg <= '1' when avSStateReg="10000" else '0';
process(CLK80)
begin
if (CLK80'event and CLK80='1') then
if (sigCLatchReg='1') then
avSigCReg(0)<= sigCReg(13) & sigCReg(13) & sigCReg(13) & sigCReg(13) & sigCReg;
for I in 1 to 9 loop
avSigCReg(I) <= avSigCReg(I-1)+ (sigCReg(13) & sigCReg(13) & sigCReg(13) & sigCReg(13) & sigCReg);
end loop;
end if;
end if;
end process;
process(CLK80)
begin
if (CLK80'event and CLK80='1') then
if (sigSLatchReg='1') then
avSigSReg(0)
<= sigSReg(13) & sigSReg(13) & sigSReg(13) & sigSReg(13) & sigSReg;
for I in 1 to 9 loop
avSigSReg(I) <= avSigSReg(I-1)
+ (sigSReg(13) & sigSReg(13) & sigSReg(13) & sigSReg(13) & sigSReg);
end loop;
end if;
end if;
Ws0<=avSigcReg(0);WS1<=avSigcReg(1);WS2<=avSigcReg(2);WS3<=avSigcReg(3);WS4<=avSigcReg(4);
Ws5<=avSigcReg(5);WS6<=avSigcReg(6);WS7<=avSigcReg(7);WS8<=avSigcReg(8);WS9<=avSigcReg(9);
end process;
end Behavioral;
I have simulate it, it looks like adding the ten value last received from the AD. The divider is not occured in this part of code(or just discarding). I wanted to know more about a shift register and an adder tree you have mentioned.
Thanks for your reply. I'm a new learner so that I don't understand why this code is messy.
Honored Contributor
