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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to make a averager in VHDL

I have just readed a piece of VHDL code. It is used to average the signal value from AD(14 bit). The code i write below here： process(CLK80) begin if(CLK80'event and CLK80='1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes，Thanks for your reply .I have made simulation for this code.It looks like just summing the ten numbers last received from the AD.