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Altera_Forum
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13 years ago

how to keep hearchie during the analysis & synthesis

hello , i synthesize my design by running quartus analysis & synthesis then i generate the verilog quartus mapping file VQM to obtain a synthesized netlist. Unfortunetly the VQM generated is no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

hello ,

quartus can generate vqm for third party tool such as amplify ,precision with commande quartus_eda

i use the vqm file in order to do the design partitionning before loading the bitstreams on FPGAs.

so i 'am looking for a hierarchical generated vqm file .