Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- But I think that will limit the processing speed to 20 MHz again, right? What do you mean by 'sharing resourse'? --- Quote End --- Your logic is running rocket high at 100MHz so every one clock period of 100 you get 1 sample of ADC. you got 99 left and can be used for whatever purpose. If your 100 clk is unrelated to adc clk then you need dc fifo else you don't.