How to interface 1 MSPS ADC with processing module?

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I'd suggest you don't need a FIFO - although a FIFO is a perfectly good way of solving it.

Assuming 1.25MSPS you're generating a new reading every 800ns. With a 100MHz 'processing' clock that gives you 80 clock cycles with which to process the data before the next sample arrives. That's plenty fast enough to allow you to oversample the ADC's clock domain to determine when a new sample is available. No FIFO needed.

Cheers,

Alex

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What do you mean by 'oversampling the ADC's clock domain'? Inserting zeros between samples?