How to interface 1 MSPS ADC with processing module?

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ADC clk is 20MHz, it gives samples every 16 clks so ADC data speed is 20/16 = 1.25 Msps but you are saying it is 1Msps.

either way you can use fifo written to at 1Msps rate and read out at same rate. then process at that rate using clk 100Mhz enabled at data rate or even you can share resource at such high clk rate available to you.

I don't think you need any rate conversion using upsamplers.

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But I think that will limit the processing speed to 20 MHz again, right?

What do you mean by 'sharing resourse'?