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liuyz's avatar
liuyz
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7 years ago

How to install tools for OPAE/HLS workflow under Intel Acceralation Stack?

Due to project needs and tools available, we are seeking help on setting up development for OPAE/HLS workflow under Intel Acceralation Stack framework for either PAC N3000 or A10 GX card.

Currently, in our mind, we would like to

1/ develop acceralation kernel using HLS

2/ verify the hardware design standslone with ModelSim FPGA Starter version

3/ generate .gbs file for AFU

4/ develop host logic with OPAE

5/ run/verify design under Intel Acceralation Stack

We tried to setup the environment but still not working. The exact tools and versions we installed are as below:

1/ Intel Acceralation Stack v1.2 (this includes Quartus Prime Pro v17.1.1, OPAE v1.1.2)

2/ HLS v19.3

3/ Intel FPGA ModelSim Starter v17.1.0

4/ OS is Ubuntu 16.04

5/ GCC 5.4

We followed the Intel High Level Synthesis Compiler - Getting Started Guide (UG-20036 | 2019.09.30), but when tried for 

make test-fpga

, build failed. Error log is in the attachment.

(note that make test-gpp, or test-x86-64 are all okay and can be verified.)

Could you help to confirm if the above flow/understandings are correct?

How should I proceed next?

Thanks a lot.

8 Replies

    • liuyz's avatar
      liuyz
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      7 years ago

      Thank for your reply.

      Yes, I have installed 32bits support on Ubuntu for ModelSim, and it seems I can start it standalone. But I will give RHEL a go.

      For GCC, the installed one on my system is v5.4, and I set i++ to use the system gcc. For the v4.7.4 in the log, I have no idea, and it looks like from the ModelSim install folder. We use v17.1 ModelSim, and gcc 4.7.4 is part of the installation folder.

      I think these are also parts of my query, which is the env doesn't hookup.

      Have you successfully setup the HLS/OPAE flow?

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
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    7 years ago

    Hi,

    According to the link https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/intel-fpga-pac-n3000/getting-started.html, you may follow the Intel Acceleration stack version, Quartus Prime version and system requirement, since there is a difference in hardware configuration in using different acceleration stack version.

    For your information, the OPAE version created for Intel FPGA PAC N3000 is not compatible with any other Intel FPGA PAC.

    The "make test-fpga" problem might be regrading to the LD data path for simulation is not correct. You may have an extra steps to have the simulation working replace ld from 'intelFPGA_pro/17.1/modelsim_ae/gcc-4.7.4-linux/libexec/gcc/i686-pc-linux-gnu/4.7.4/ld' to the one in 'usr/bin/'. After change the LD data path, the simulation will be run successfully.

    I had send information related to the Intel PAC N3000 card to your email.

    Can you check your email?

    Thanks

    • liuyz's avatar
      liuyz
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      7 years ago

      Thanks Mylee, we are trying on a new machine with RHEL 7. Will let you know how we go with it.

      By the way, what do you exactly mean by "the OPAE version created for Intel FPGA PAC N3000 is not compatible with any other Intel FPGA PAC."? Is this for the host or the AFU?

      Thanks a lot.

    • liuyz's avatar
      liuyz
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      7 years ago

      Thanks, got it.

      So, the AFU park is reusable between PACs, right?

  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi,

    I am not sure what is AFU park.

    The HLS AFu design code should be can used in different FPGA.

    Thanks

    • liuyz's avatar
      liuyz
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      7 years ago

      Thanks for confirming.