Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- instead of using a text file, generate a VHDL package instead: Then you can re-write or modify the package without having to worry about the source. The package could be generated via the same method you generated your ram_init.txt --- Quote End --- when writing reusable code including a package makes things a bit more complicated. if i want to use the code multiple times with different parameters, i have to copy the VHDL source and the package to new files. if i could initialize things from text files i could pass a string generic to the source and not copy any files. oh well. :o