How to initialize content of a RAM without using Megawizard

Reply from Anthony in mysupport (by the way thank you)

--- Quote Start ---

The reason of the failed RAM initialization in your design is that File I/O operations in VHDL aren’t supported to be synthesized in Quartus II. Due to this the RAM initialization with a text file isn’t supported in VHDL for inferred RAMs. You may refer to the section “Specifying Initial Memory Contents at Power-Up” on page 6-27 of Quartus II Handbook Version 9.0 Volume 1: Design and Synthesis to learn how inferred RAM can be initialized in VHDL.

BTW, Quartus II supports the $readmemb and $readmemh system commands in Verilog to initialize memories with a text file. You may consider implementing your design in Verilog to meet your design requirement.

--- Quote End ---