Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHello people,
@FvM it is why i opened this topic in the Altera's forum. The synthesis output tdf file (AHDL) is generating an initiliaze file (mfi) for the RAM. When I don't initilialize the RAM signal RAM : RamType; instead of signal RAM : RamType := InitRamFromFile("ram_init.txt"); no initiliaze file (mfi) for the RAM is created. For your information, XST which is the xilinx's synthetiser is working correctly with this manner. I raise my issue to altera via mysupport. So wait and see... Thanks for your help :)