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Altera_Forum
Honored Contributor
10 years agoHow to initialize a signal without any loops
Hi, I'm very new at learning VHDL and have some trouble dealing with unwanted results of the project I've been working on. I'm designing a state machine for my school project. What I want to ma...
Altera_Forum
Honored Contributor
10 years agoInitial value could be achived via signal that perfom reset/clear function.
Can you draw ASM chart for project and compare it with code. Usually you create design starting from ASM chart, then you write code, you allow to compile it and compare your desires (ASM chart) with results (state machine transition, hardware structure, modeling in sims)