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Altera_Forum's avatar
Altera_Forum
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9 years ago

how to incorporate 2 cycles of latency

hello fellow vhdl coders I have been away from VHDL for over 2 years and I have a question which I am struggling to complete. does anyone know how to incorporate 2 cycles of latency into my vhd...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

inside that process or in another clocked process write:

--z to be signal, not output

z_1d <= z;

z_2d <= z_1d; -- this should be output