Forum Discussion
EIbra
New Contributor
New ContributorHow to `include file in the IP Verilog source?
I have project with Qsys and custom IP IP has main Verilog file comm_channel_control.sv with lines module (...)
...
`include "comm_channel_control_params.svh"
...
endmodule main module and "comm...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorThanks for sharing the solution, Which will help the community.
