Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

How to improve the frequency of the running clock of FPGA?

Hi, After I compile my OpenCL FPGA code, I find the frequency of the running clock of the kernel is about 130MHz, how to improve it? Thanks!
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

There is no direct control over operating frequency in OpenCL. Loop-carried dependencies and complex loop exit conditions reduce operating frequency. Also if your design is large with a high logic utilization count, that will complicate routing and reduce operating frequency.