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Altera_Forum
Honored Contributor
17 years agoi found another solution;
module ust_module(clock,a,b,result,overflow,underflow);
input clock;
input a,b;
output result;
output overflow,underflow;
wire c;
wire d;
mult2 carpici2(
.aclr(),
.clk_en(1'b1),
.clock(clock),
.dataa(d),
.datab(64'h4000000000000000),
.denormal(),
.indefinite(),
.nan(),
.overflow(overflow),
.result(result),
.underflow(underflow),
.zero());
mult carpici(
.aclr(),
.clk_en(1'b1),
.clock(clock),
.dataa(c),
.datab(64'h4000000000000000),
.denormal(),
.indefinite(),
.nan(),
.overflow(),
.result(d),
.underflow(),
.zero());
adder toplayici(
.aclr(),
.clk_en(1'b1),
.clock(clock),
.dataa(a),
.datab(b),
.denormal(),
.indefinite(),
.nan(),
.overflow(),
.result(c),
.underflow(),
.zero()) ;
endmodule it works also but there is another problem happens, i want to connect the result to input b but i want to add a d-flipflop on the line. or an shiftreg but these ffs are using 8 bits but my output bus is 64 bits. i want to use a mux-demux but i couldnt find any demux megafunction in quartus. Are there any option to change the bit selection in dff or shiftreg, or any demux example that i can use?