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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to implement two-dimensional array using HDL?

I need to creat many tables in FPGA, and these tables are used to store two-dimensional array data.

For example, when I get (x,y) value and then find the coordinate according this (x,y) value.

These table also can be updated, so they must be strore in "RAM" (not in "ROM").

But I found some comments about the two-dimensional array, which said that two-dimensional array is just used on simulation, for two-dimensional array couldn't be synthesized to circuit. If so, how to implement my application in my FPGA? Does ALTERA have some functions (or mega core) like this?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    A 2-D array (N,M) can be simply mapped to a 1-D array (N*M). If N and M are both powers of two, just concatenate the address vectors. In so far, no special functions are needed.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    A 2-D array (N,M) can be simply mapped to a 1-D array (N*M). If N and M are both powers of two, just concatenate the address vectors. In so far, no special functions are needed.

    --- Quote End ---

    Dear FvM:

    Good idea!

    But i have another question. For my application, the N=M=9, the QII can only implement memory which depth is below 65536. It seems that i shouldn't merge samll memorys to a big one, for i must find my result according N&M's value.:cry:
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    why cant you round N and M up to 16? then you can use sensible addressing and concatenate N and M?