How to implement a System like this easily using Altera Tools of my DE1-SOC?

It sounds like you are constructing a prototype and maybe this is your first time doing any FPGA development.

In that case, I would suggest just doing as much as you can on the ARM Linux side (transferring the image, converting it if necessary, etc) and then write the image to the FPGA side. On the FPGA side, just implement a single Qsys IP component with an Avalon-MM Slave interface, and then inside there write your Verilog to receive the pixels one at a time and produce the results one at a time.

There are several appnotes and training videos you could/should run through to get an idea of what is involved. Here is one example: http://wl.altera.com/education/training/courses/osoc1000

After you have the algorithm running OK, you'll likely find that software moving the image data is the bottleneck. Adding a DMA would be a small incremental change on top of that.