How to implement a System like this easily using Altera Tools of my DE1-SOC?

You sound like you are still very confused.

If you are writing your own HDL, then you probably wont need a NIOS. To generate a NIOS you need to generate in QSYS (QSYS is the Quartus System Builder application). Without QSYS - you just write your HDL and away you go.

From your description, it sounds like having 4 processing elements would be a waste of resources. With such a small image, you could easily read the whole image in via a single stream and process it with a signle logic block. But you havent really given us the algorithm you are using.

but there are many unanswered questions that need to be answered before you continue:

Why would you only process 1 pixel at a time?

why cant you just stream in the picture?

are you processing a single image or video?

where does the image come from and how does it get loaded?

what external interfaces are you going to use?

what clock speed are you going to use to get the data throughput you need?

Without specifying data rates and interfaces, it's pointless trying to design the system as they can affect the entire design.