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Do you want to write software or HDL?
If you want to write HDL, then create a new Qsys component IP block and instantiate it four times. Give it however many Avalon-ST ports necessary to make your connections. Use e.g. Modular SGDMA to read the frame data out of RAM and supply it to the components, and have a NIOS with software to control the flow and manage the DMA.
If you want to write software, something as simple as a large shared on-chip RAM with (4) NIOS connected directly to it would work. Qsys would automatically take care of arbitration/contention, but since you don't have a speed requirement this is fine.
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Thank you. By writing software or HDL, do you mean whether to use C or Verilog? I'd like to use HDL Verilog as possible. So I guess the first option is the correct.
Excuse my noobish, when you say to create the QSYS component IP, would this depend on an specific hardware, depending on the NIOS-II? Because I'd like to run the cores by FPGA itself not by the processor NIOS, board resources would work as "auxiliary" (read and supply image from ram, etc).
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