how to implement a large memory on DE2 KIT ?

IF you want to use SDRAM or SRAM on DE2 Kit, you need to build your own an interface to there devices. However, it will be so complex but it's the the only way if you want to design a CPU with a large memory. In other word, you need to design a controller to interact between input and output data and this thing result in you have to truly understand the protocol read out and write in them.

Honestly, I haven't yet finished this controller so I can give them to every one in detail. However, If you want to reference, you can surf on the internet one page which possibly useful for this design. Here it's :

http://www1.cs.columbia.edu/~sedwards/apple2fpga/

The most important thing I found that If you intend design a CPU , dont be foolish to use NIOS-SOPC, you will depend on most it's architecture and that core and especially to avalon bus, it makes me confuse the FPGA architecture. Altera basically expect that we use their IP core as well as NIOS CPU so their tutor just trick our feel that it's snobbish but the fact that it is useless( at least in this design) and they transform us to their absolutely depended customer.