how to implement a large memory on DE2 KIT ?

In several days, I have found some way to use SDRAM for my CPU, but it seems to be impossible.

Feeling disappoint, I decide to jot down something on this thread. :( !!!

- I try to use SDRAM controller of SOPC builder, but it needs avalon bus master.

look at all my process to design my CPU:

I have designed a Data Path and Control Path which further information below:

Datapath:

- ALU : 16 simple intructions

- PSR PC, IR register

- regiter file: 8 registers

- mem (64K*16bits)

- interupt module

Cotrol Path:

- a list of state machine and decoded instructions

type of CPU is Von neumann/princeton ( it shares data and instruction memory)

the method to deal with MEM is so complex, especially when I need to implement on DE2 Kit

It's clearly that I can't use M4K cell of Cyclon II because the synthesis is so long and waste resource. So the solution is SRAM or SDRAM integeratied in DE2 and this thing obey me need a SDRAM controller.

I have read some material relating SDRAM and I know that it's rather complex and need to well control with PLL. Moreover, in the level of hardware, I also need to take care AVALON bus.

It sounds good, isn't it ?

As I have mention above, I try to use SOPC to utilize available sdram controller. However, it can't work if not absence of NIOS II. SOPC builder seems to another aspect of design. So hopeless with it !!! I have to follow several procedure of SOPC builder and it not permit user control avalon bus, or I dont know how to do this work.