How to I feed a single input clock pin to 2 PLLs

Sree, Thank you for responding, even if it is 2 months late. I don’t think you understand the question. Let me clarify: I have instantiated an EMIF IP for DDR4 memory. In that IP is an IOPLL and that expects a reference clock on a pin. I also have an additional IOPLL in the FPGA. I would like to connect its reference clock input to the same pin, but when I do the fitter gets an error. Note that the EMIF actually replicates its IOPLL in all the banks used by the DDR4 which in my case is 3 banks. I have found that I can force the signal on the reference clock pin to be a global clock, and then I am able to avoid the fitter error. It appears there is something special about how the tools want to hook up the reference clock to the EMIF PLL and it does not want the clock to go anywhere else. My question is, what is the best way to hook 2 PLLs up? One possibility is that for an EMIF IP, you should never connect its reference clock to anything else. Another possibility is that you need to do XYZ in order for the fitter to work. If the answer is XYZ, please tell me what XYZ is. I am just trying to understand why things are the way they are. This is not documented anywhere that I can find. Bill