Altera_Forum
Honored Contributor
17 years agoHow to gnerate a FIFO with these parameters
I want to generate a 32x5 fifo for my design with the following parameters. I have the older version of this FIFO but is actually gnerated from altdpram megafunction (which I can percieve),but I have also found out that altdpram is no longer supported instead altsyncram is supported ,but I cannot afford changing the parameters otherwise I have to change the whole design
defparam fifo32x5.LPM_WIDTH = 5; defparam fifo32x5.LPM_WIDTHAD = 5 ; defparam fifo32x5.INDATA_REG = "INCLOCK" ; defparam fifo32x5.WRADDRESS_REG = "INCLOCK" ; defparam fifo32x5.WRCONTROL_REG = "INCLOCK" ; defparam fifo32x5.RDADDRESS_REG = "OUTCLOCK" ; defparam fifo32x5.RDCONTROL_REG = "OUTCLOCK" ; defparam fifo32x5.OUTDATA_REG = "UNREGISTERED" ; defparam fifo32x5.INDATA_ACLR = "OFF" ; defparam fifo32x5.WRADDRESS_ACLR = "OFF" ; defparam fifo32x5.WRCONTROL_ACLR = "OFF" ; defparam fifo32x5.RDADDRESS_ACLR = "OFF" ; defparam fifo32x5.RDCONTROL_ACLR = "OFF" ; defparam fifo32x5.OUTDATA_ACLR = "OFF" ; defparam fifo32x5.LPM_HINT = "USE_EAB=ON" ; However while compiling this module in Precision( a mentor tool ) followed by pnr in Quartus II ,Quartus II issues a warning Warning: Assertion warning: altdpram does not support Stratix II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Stratix II devices Plz help..