How to force typical corner for StratixII

I'm currently using stratixII FPGA, EP2S180F1508 for prototyping and validating IP's and system on chip before silicon.

I'm struggling against timing analysis. The target is 60Mhz. In slow corner violation is 6 ns, and in Fast corner the slack is +6ns.

As i'm using the FPGA in typical temperature, is there anyway to set a typical operating conditions in Quartus ?

I can't find it.

The operating settings and conditions seems to be precalibrated to FAST and SLOW, and no way to change them ?

If this is not possible, is there anyway to hack the altera librarie to add an operating condition ?