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Altera_Forum
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12 years ago

How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I remember someone saying that it takes time to get values into and out of the DSP blocks - so to do a multiple in logic probably requires that you add another pipeline stage (or two) somewhere.

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Yes, Ive seen the fitter have no problems with the DSP blocks themselves, but then decides to put the next/previous register to the DSP half way across the chip to move it closer to the next/previous bit of logic. So adding in redundant pipeline stages pre/post DSP gives the fitter a bit of extra leeway on the timing.

You can get the same problem with RAM Blocks too.