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I didn't yet hear any results when enforcing logic implementation of the constant multipliers for the present problem.
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Sorry for the lag, but I've been fighting a couple different issues.
Enforcing the logic implementation removes the multiplier usage but loses significant speed. I would have to hand code a compression tree to win back enough speed. I may do that, at some point. If so, I will add to this post.
However, unless I hit a speed wall, I probably won't do that. I'm finding that I am more than a bit underwhelmed at the speed performance of the Arria V's. I did not expect 250+MHz in Verilog to be this problematic in a 28nm technology chip.
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