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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to force Quartus to synthesize constant mutiplies

I've got a decimator block written in Verilog. It's the standard structure: flops, then constant multiplication, then an accumulate tree. However, Quartus is using the DSP blocks for the multi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

As a point of reference, Stratix V now allows each DSP block to have 8 fixed coefficients that can be muxed from coeff_sel lines, and if Im reading correctly the coefficients can be up to 27bits. This might actually be a way to avoid the Ram based multipliers that ive seen used for higher speed designs when the multiplier value is fixed.