How to fix State <name> contains multiple transitions, but more than one transition equation are TRU

Tip: learn to code in HDL (Verilog or VHDL) instead of relying on the State Machine Editor/Wizard. You'll learn a lot more.

But regarding your design, can you show the code generated by the tool? Are these supposed to be 2-bit wide inputs and 3-bit wide outputs, or is that just how they are represented numerically in the tiny diagram you've attached?

Also, you're setting output ports to the input ports? Output Value is usually a value (a number).

Show the code output from the SME. That will make it much easier to understand what you've done here.