Forum Discussion
KhaiChein_Y_Intel
Regular Contributor
7 years agoCan you report timing for PLL_1|pll_clk_manager_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk to see the failing paths?
Can you report timing for PLL_1|pll_clk_manager_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk to see the failing paths?