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AHorn4
New Contributor
New ContributorHow to fix large number of hold violations for Cyclone V GX in Quartus II?
My Cyclone V GX design compiles with no setup or hold violations in the two slow models but contains a large number of very small (< 0.2ns) hold violations in the two fast models. After investigating...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorCan you report timing for PLL_1|pll_clk_manager_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk to see the failing paths?
