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Altera_Forum
Honored Contributor
7 years agoI wish it was, but how? I am not doing anything to change the board myself, so how can I make it for the same device? This is the command I use for compilation:
aoc -o t_device -v -I/x/inc -I/x/bin2 -I/y/intelFPGA/17.1/hld/include/kernel_headers -board=de1soc_sharedonly -profile -high-effort -fp-relaxed -fpc -seed=3 /x/device/device.cl I suspect the Terasic board support package might be incomplete because the board_spec.xml file does not contain a line containing 5CSEMA5F31C6, only this one: <device device_model="5csxfc6d6f31c8es_dm.xml">. File board_spec.xml: <?xml version="1.0"?>
<board version="14.1" name="de1soc_sharedonly">
<compile project="top" revision="top" qsys_file="system.qsys" generic_kernel="0">
<generate cmd="ip-generate --component-file=system.qsys --file-set=QUARTUS_SYNTH --output-directory=system/synthesis --report-file=qip:system/synthesis/system.qip --jvm-max-heap-size=3G"/>
<synthesize cmd="quartus_sh --flow compile top -c top"/>
<auto_migrate platform_type="c5soc" >
<include fixes=""/>
<exclude fixes=""/>
</auto_migrate>
</compile>
<device device_model="5csxfc6d6f31c8es_dm.xml">
<used_resources>
<alms num="1080"/><!-- ALMs used for LUT logic + ALMs used for LUT logic and registers-->
<ffs num="1908"/>
<dsps num="0"/>
<rams num="20"/>
</used_resources>
</device>
<!-- One DDR3-800 DIMM, 256-bit data -->
<global_mem max_bandwidth="6400">
<interface name="acl_iface" port="kernel_mem0" type="slave" width="256" maxburst="16" latency="240" address="0x00000000" size="0x40000000"/>
</global_mem>
<host>
<kernel_config start="0x00000000" size="0x0100000"/>
</host>
<interfaces>
<interface name="acl_iface" port="kernel_cra" type="master" width="64" misc="0"/>
<interface name="acl_iface" port="kernel_irq" type="irq" width="1"/>
<kernel_clk_reset clk="acl_iface.kernel_clk" clk2x="acl_iface.kernel_clk2x" reset="acl_iface.kernel_reset"/>
</interfaces>
</board>