How to find output of variable latency modules
Instantiating Altera Megafunctions in my code, specifically Altera Floating Point megafunctions I find that these megafunctions don't have an 'output valid' or 'done' output bit with which I can ascertain whether or not the module has finished processing. I thought that since the latency will be fixed I'll assign a counter and manually raise a signal everytime number of fixed latency cycles of a given module are completed and at that time take the output. But now running testbenches on these modules I find that the latency is also variable i.e. at times the blocks produce the output pretty quickly in maybe 5 clock cycles and at times they can take longer 14-15 clock cycles for certain inputs. What mechanism can I use to find if the block has finished calculating the output?
Any help is most appreciated. Thanks.