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I've been charged with taking over an fpga design from another engineer. This design has 17 clock domains with numerous crossings among its 43 rtl modules spread over 5 levels of hierarchy. I am concerned that some of the clock crossings are not being handled properly, and because the design is full of code evolved from prior designs, I'm facing a daunting challenge to discover and analyze all the crossing points.
Is there way to get TQ to report every source/destination register pair that
doesn't lie in a single domain? I'm thinking of a report that has something like: from node, to node, launch clock, and latch clock. I could then scan the list and quickly see where to go in the design to check the logic. If there isn't a ready-made means to generate that report, does anyone know a way to "coerce" that information out of TQ?
Any guidance is much appreciated.
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Hi,
which Timing Analyzer do use ? TimeQuest ?
Kind regards
GPK
Honored Contributor
