How to export signals from a UART (TX,RX) in verilog

Hi,

I was hoping somebody could tell me how to correctly export signals from a UART in a NIOS II.

I created a NIOS using QSYS with switches, lights and a UART. I have exported all of these block so that I can assign them pins.

My top level verilog code where the NIOS is instantiated is located.

My question is - how to I export the signals for the UART (TX, RX) which has both input and output?

My code below, is giving an error on

.uart_export(TX,RX),

, as using a comma is incorrect.

I need to do this so that I can assign the pins to GPIO on development board.

Thanks

// Implements a simple Nios II system for the DE-series board.
// Inputs:      SW7-0 are parallel port inputs to the Nios II system
//                  CLOCK_50 is the system clock
//                  KEY0 is the active-low system reset
// Outputs:    LEDR7-0 are parallel port outputs from the Nios II system
module
lights (CLOCK_50, SW, KEY, LEDR, TX, RX);
input
CLOCK_50;
input
  SW;
input
  KEY;
output
  LEDR;
input
RX;
output
TX;
// Instantiate the Nios II system module generated by the Qsys tool:
nios_system  NiosII  (
.clk_clk(CLOCK_50),
.reset_reset_n(KEY),
.switches_export(SW),
.uart_export(TX,RX),
.leds_export(LEDR));
endmodule