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Altera_Forum's avatar
Altera_Forum
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8 years ago

How to ensure multiplexer priority levels coded in VHDL

Hi, How to ensure a value "CAFE" on the register Reg_In with the RTL code:Reg_In <= X"CAFE" when A = '1' else In_1 when K = '1 else In_2 when L...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

During synthesis and fitting the whole design is taken into account.

This results in the behavior: "The low Reg_In byte is always set to "FE", the high byte is not set to "CA" sometimes."

The question is: how can this be avoided? In VHDL or with other options in Quartus?