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Altera_Forum
Honored Contributor
14 years agothank you alot for the reply i alreday use the CLOCK_50 in my VHDL design instaed of clk that i used , but it is still the same, i think i need to make some dely between every state as the frequncy is 50Mhz(200 ns) and can not be recognized by human being, the machine moves from state a and in the next rising edge , it moves tio state B and then C, so can not see flashing