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JPye's avatar
JPye
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7 years ago

How to eliminate sporadic errors on Stratix-V designs?

Our company makes products using a board we designed which has two Stratix-V parts. We have various FPGA designs that operate on this board already. We were recently motivated to change and add some ...
KennyT_altera's avatar
KennyT_altera
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7 years ago

Hi Johnm

Jan point out some important point, you also need to check your constrain is written correctly and all the timing closed before do the hardware testing.

Thanks

JPye's avatar
JPye
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7 years ago

KTan9,

As far as we know our timing constraints are correct. And we only test builds with timing closure. The core voltage seems stable when we measure it on a scope and temperature does not read as excessive.

Yesterday I posted more details. I am not sure if you saw them since my posts seem displayed out of order on the web page. Based on those details do you have any more specific suggestions on what to review?

We can have an expert review our constraints if that is possible.

Thanks,

John