Forum Discussion
SPraj4
New Contributor
New Contributorhow to "duplicate nodes" and "reduce levels of combinational logic" to remove negative slack in timing analysis Quartus??
I am trying to design ddr3 interface using Qsys in Quartus Prime Lite Edition for cyclone V GT (5CGTFD9E5F35C7) Development board. While running timing analysis, I am facing setup and hold violation...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi, one more thing is to compare your design QSF vs example design QSF. Spot out any setting that potentially cause the timing violation. the slack value is huge, there should be something obvious that cause the violation.
