Forum Discussion
SPraj4
New Contributor
New Contributorhow to "duplicate nodes" and "reduce levels of combinational logic" to remove negative slack in timing analysis Quartus??
I am trying to design ddr3 interface using Qsys in Quartus Prime Lite Edition for cyclone V GT (5CGTFD9E5F35C7) Development board. While running timing analysis, I am facing setup and hold violation...
sstrell
Super Contributor
Super ContributorI mean you should take the example project, make sure it works, then customize it for your own use. Use the project itself as a base. Don't try to copy the settings you see in the example project into your own because you'll inevitably miss something.
#iwork4intel
