how to "duplicate nodes" and "reduce levels of combinational logic" to remove negative slack in timing analysis Quartus??

Yes I used that download but not compiled "golden top" . Instead I opened "q_sys_hmc.qsys" from "board_test_system" (examples\board_test_system\qts_ddr3\c5gt_ddr3\ ). From there opened ddr3 uniphy IP and made a preset with exactly same parameters and settings.

And further added that preset to my project and compiled it and got synthesis errors. You said that:

"Since the download is for an older version of Quartus, you would probably need to update the IP, but that project should be the starting point."

when I opened the example project I updated the IP, but what you mean by "that project should be the starting point"??