how to "duplicate nodes" and "reduce levels of combinational logic" to remove negative slack in timing analysis Quartus??

Those solutions are not typically what you would need to do to solve timing issues in an EMIF IP, only if the timing issues extended into the internal logic of your design. Are you using the hard or soft IP? Go back into the IP Parameter editor and double-check all your settings and timing values. Since you say you are using a dev kit, you should try using the example EMIF design that should be included with the download for the kit. The IP settings in the included design would already be set up correctly for that particular kit.

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