Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

How to do synthesis with Synopsys design compiler?

Hi, I would like to know how I can use the Synopsys design compilers to do synthesis for a specific Verilog module? The primary reason is to do register re-timing. The physical register re-t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Instead of using design compiler, you need synplify for FPGA fabric. Although theoretically Design compiler could work with library cells, it doesn't know about the LUT's of FPGA's. So it wouldn't do as good of a job.

Synopsys bought Synplicity a few years ago. Before that they had a tool called FPGA Compiler that was based on Design compiler, but it didn't do as well as synplicity's synplify pro.

Pete