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hi,kaz."number (2): How do we relate tSU/tH of external device to data/clk relation. A complete mystery to me."
I'm confused too.
This question , for you, almost 3 years pass,I think you must have understood it. Could you show me how to relate tSU/tH of external device to data/clk relation?
according to the altera document"AN433:Constraining and Analyzing Source-Synchronous Interfaces"
set_input_delay -max UI-tSU_ext
set_output_delay -min tH_ext
it's difficult to understand for me. Instead ，the case(1) you mentioned using tCO to set_input_delay is much easier 。Then the question can also change to find out the relationship of tCO and tSU/tH of external device's output port .In my opinion, for the output port of external device ,tSU/tH means the output data will be stable during the {tSU,tH} window,right? So, after the launch clock edge,the data must be transport to the output port before tH of the external device,otherwise the data will be
unstable.So, we get tCO_max=tH.
for the similar situation,tCO_min = -tSU.
then,we should get:
set_input_delay -max tH_ext
set_output_delay -min -tSU_ext
what do you think?
thanks.
Andrew
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Yes I think I understood case(2) after 3 years!
The problem was that they don't tell tSU,tH of which device. I now assume that they mean those given by external device datasheet as requirement on receiving device . i.e. some devices give them instead of tCO(which makes more sense). In other words the manufacturer tells you that they require fpga tSU/tH to be those values. hence the equations become:
-max UI-tSU
-min tH
This is basic if you draw clock waveforms and remember that tSU relates to current latching edge while tH relates to previous latching edge.
Edit:
However, admittedly I don't see how external device tCO = UI-tSU(of fpga) if manufacturer does not know about UI i.e. clock speed used.
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