How to determine the maximum and minimum of input delay?

li_polaris, can you explain your question on thumbnails showing input and output delay? Looking at the output delay, the clocks don't move at all. They are 10ns and "ideal". The set_output_delay -max 4.0 states that the external max delay is 4ns. On a simple level, that means the FPGA needs to get it's data out within 6ns so that, after the external 4ns delay is added, it can be captured by the latch edge at time 10ns. Now, where does that 4ns come from? Generally it is the data's board delay + Tsu of the external device. For example, if the board delay was 500ps, and the Tsu was 3.5ns. (A Tsu of 3.5ns says the data needs to be present 3.5ns before the clock, which is identical to saying there is a 3.5ns delay on the data path inside the external device, compared to the clock path in the external device). Now, that hasn't accounted for any board level clock skew between the FPGA and the external device. The guide should go into that later on in that section, but let me know if it's not clear. Any suggestions you have for improvement or something that's not clear would be welcome.